verilog數(shù)字鐘

1、I武漢理工大學(xué)課程設(shè)計(jì)——基于基于VerilogHDL的簡易電子鐘設(shè)計(jì)的簡易電子鐘設(shè)計(jì)摘要Verilog是廣泛應(yīng)用的硬件描述語言，可以用在硬件設(shè)計(jì)流程的建模、綜合和模擬等多個階段。隨著硬件設(shè)計(jì)規(guī)模的不斷擴(kuò)大，應(yīng)用硬件描述語言進(jìn)行描述的CPLD結(jié)構(gòu)，成為設(shè)計(jì)專用集成電路和其他集成電路的主流。通過應(yīng)用VerilogHDL對簡易電子鐘的設(shè)計(jì)，達(dá)到對VerilogHDL的理解，同時對CPLD器件進(jìn)行簡要了解。本文著眼于使用EDA開發(fā)工具實(shí)現(xiàn)簡易

2、電子鐘的設(shè)計(jì)。隨著微電子技術(shù)，計(jì)算機(jī)技術(shù)的不斷發(fā)展和完善，EDA技術(shù)已日趨成熟逐漸成為現(xiàn)代電子技術(shù)的IIIAbstractIswidelyusedVeriloghardwaredeionlanguagecanbeusedinhardwaredesignprocessmodelingsynthesissimulationphases.Withtheconstantexpansionofthehardwaredesignhardwarede

3、ionlanguagetodescribetheapplicationoftheCPLDarchitectureadesignofASICsotherICsmainstream.ThroughtheapplicationofVerilogHDLdesignofsimpleelectronicclocktotheunderstingofVerilogHDLwhileabriefunderstingoftheCPLDdevice.Thisa

4、rticlefocusesontheuseofEDAtoolstoachievethedesignofsimpleelectronicclock.AsmicroelectronictechnologycomputertechnologycontinuestoevolveimproveEDAtechnologyhasmaturedgraduallybecometheheartofmodernelectronictechnology.EDA

5、technologyistothecomputerasatooldesignerinEDAsoftwareplatfmwithcompletehardwaredeionlanguageVerilogHDLdesignfilesautomaticallybyacomputertocompletethelogiccompilersimplificationsegmentationintegrationoptimizationplacemen

6、troutingsimulationupadapterchipfthespecifictargetcompilationmappingprogramminglogictodownloadsoon.EDAtechnologiescircuitdesigngreatlyimprovestheefficiencyoperabilityreducingthelabintensityofthedesigner.EDAtechnologyiswid

7、elyusedinmachineryelectronicscommunicationsaerospacechemicalmineralbiologicalmedicalmilitaryotherfields.OnAlterasFlex10KseriesEPF10K10briefAlteraCpationSoftwareMaxplusⅡBriefintroductionapplicationofVerilogHDLdesignofthee