avs和h.264雙模解碼器soc混成架構(gòu)的設(shè)計(jì)與研究

1、上海交通大學(xué)碩士學(xué)位論文AVS和H.264雙模解碼器SoC混成架構(gòu)的設(shè)計(jì)與研究姓名：王忠平申請(qǐng)學(xué)位級(jí)別：碩士專(zhuān)業(yè)：軟件工程指導(dǎo)教師：祝永新20080101上海交通大學(xué)工程碩士學(xué)位論文 第 II 頁(yè) ABSTRACT As H.264 and AVS video compression technology are widely used nowadays and standard the researches on H.264 an

2、d AVS are more and more, one target is to achieve the high speed of compression on the basis of ensuring the encoding quality is not influenced. The ASIC design about H.264 decoder is successful in china and abroad, and

3、AVS decoder is new China video compression technology, which has wide future. But in comparison, encoder is more complicated in algorithm and ASIC design so that the whole world is still researching on it. As for this pr

4、oject, the target is to find a reasonable path to reuse IP hardware modules for decoding two different video compression standards streaming. We divide the software and hardware by analyzing the timing cost of H.264 and

5、AVS code. Finding out the section located at the bottom layer, much timing cost and calculating quantity, easy dividing between software and hardware, high parallel degree and low hardware spending, the architecture of s

6、oftware and hardware co-design will be realized on an ESL system simulation platform to check its function and performance, The result shows that the hardware module divided may save timing consumption by achieving the r